FPGA/ASIC Design Engineer

Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

Client has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).

This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.

* Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
* Proficient in VHDL design process and FPGA flow
* Knowledge of Ethernet, TCP/IP protocols
* Strong logic/board debug, and analytical skills.
* Excellent written, verbal, and presentation skills.

A PLUS for prior experience with:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)

VHDL Experience is required for all candidates to be considered.

* Looking for mid-senior level folks
* Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
* Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
Big Plus
*Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
*Mentor EDA CDC/Lint/AC/RDC

Required Skills:

*Derive engineering specifications from system requirements and develop detailed architect
*Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
*Generate test plans
*Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
*Silicon/FPGA bring up, characterization and production ramp/support/collateral
 
Job Location: St. Reston, VA
Input Date: 10/20/2025
Firm Name: GLOBAL TECH SERVICES
Attention: Valerie White
Address: P O BOX 161127
3455 NE LOOP 820
City, State: FORT WORTH, TX 76161-1127
Phone: 817/847-6673
800 Phone: 800/942-2376
Fax Phone: 817/847-9444
Email: vwhite@teamglobal.com
Website: www.teamglobal.com
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