FPGA/ASIC Design Engineer

Description:
Chipton-Ross is seeking a FPGA/ASIC Design Engineer for a contract opportunity in Reston, VA.

BASIC QUALIFICATIONS (REQUIRED SKILLS/EXPERIENCE):
•Possess an active SECRET Clearance.
•Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
•Proficient in VHDL design process and FPGA flow.
•Knowledge of Ethernet, TCP/IP protocols.
•Strong logic/board debug, and analytical skills.
•Excellent written, verbal, and presentation skills.
•Derive engineering specifications from system requirements and develop detailed architecture.
•Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint).
• Generate test plans.
•Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards.
•Silicon/FPGA bring up, characterization and production ramp/support/collateral.
•VHDL Experience is required for all candidates to be considered.
•Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado.
•Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA.

POSITION RESPONSIBILITIES:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE):
•Prior experience in Aerospace / Defense.
•Experience in C++ (OOP).
•Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
•Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
•Experience with Universal Verification Mythology (UVM).
•Experience with project leadership and EVM.
•High Level Synthesis (HLS) with Vivado,
•Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
•Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet).
•Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
•Mentor EDA CDC/Lint/AC/RDC.

REQUIRED EDUCATION:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
**Education MUST be accredited**

WORK HOURS:
9/80

ADDITIONAL:
Candidate must hold a secret clearance.
 
Job Number: 215862
Job Location: Reston, VA
Rate: Up to $125.00 DOE
Duration: 6 months
Input Date: 10/08/2025
Firm Name: CHIPTON ROSS
Attention: Melody Mullins
Address: 420 CULVER BLVD
City, State: PLAYA DEL REY, CA 90293
Phone: 310/414-7800 X286
800 Phone: 800/927-9318
Fax Phone: 310/414-7808
Email: mmullins@chiptonross.com
Website: www.chiptonross.com
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